Highly Reliable Design Based on Tsc Circuits

This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools.